Answers¶
Here are the answers to this year's KringleCon:
Objective 1¶
Answer - Objective 1a) Talk to Jingle Ringford
Left click on Jingle Ringford when you enter the game.
Answer - Objective 1b) Get your badge
Jingle Ringford will give you a badge if you keep talking to them.
Answer - Objective 1c) Get the wifi adapter
After talking to Jingle Ringford, a wifi adapter appears on the ground. Left click on the adapter to pick it up.
Answer - Objective 1d) Use the terminal
After you pickup the wifi adapter, talk to Jingle Ringford. Click on the terminal that appears. Type in answer
in the terminal.
Objective 2¶
Answer
Eve Snowshoes in Prague, Czech Republic.
Objective 3¶
Answer
In the wifi adapter type the following:
iwconfig wlan0 essid FROST-Nidus-Setup
curl -XPOST -H 'Content-Type: application/json' --data-binary '{ "temperature": 20, "humidity": 0, "wind":0, "windchill": 0}' http://nidus-setup:8080/api/cooler
Objective 4¶
Answer
I'm going to have some bouncer trolls bounce you right out of this casino!
Objective 5¶
Answer
ickymcgoop
Objective 6¶
Answer
cyber security knowledge
Objective 7¶
Answer
Troll_Pay_Chart.xlsx
Objective 8¶
Answer
Kindness
Objective 9¶
Answer
whiz
Objective 10¶
Answer
CGgQcSdERePvGgr058r3PObPq3+0CfraKcsLREpX
Objective 11¶
Answer
Flud Hagg Yaqh
Objective 12¶
Answer
clerk
Objective 13¶
Answer
// Note: For this lab, we will be working with QRP Corporation's CQC-11 FPGA.
// The CQC-11 operates with a 125MHz clock.
// Your design for a tone generator must support the following
// inputs/outputs:
// (NOTE: DO NOT CHANGE THE NAMES. OUR AUTOMATED GRADING TOOL
// REQUIRES THE USE OF THESE NAMES!)
// input clk - this will be connected to the 125MHz system clock
// input rst - this will be connected to the system board's reset bus
// input freq - a 32 bit integer indicating the required frequency
// (0 - 9999.99Hz) formatted as follows:
// 32'hf1206 or 32'd987654 = 9876.54Hz
// output wave_out - a square wave output of the desired frequency
// you can create whatever other variables you need, but remember
// to initialize them to something!
`timescale 1ns/1ns
module tone_generator (
input clk,
input rst,
input [31:0] freq,
output wave_out
);
// ---- DO NOT CHANGE THE CODE ABOVE THIS LINE ----
// ---- IT IS NECESSARY FOR AUTOMATED ANALYSIS ----
// TODO: Add your code below.
// Remove the following line and add your own implementation.
// Note: It's silly, but it compiles...
reg wavey;
assign wave_out = wavey;
real counter;
real increment = 125000000 / (freq*2/100);
always @(edge clk or negedge rst)
begin
if (rst==1)
begin
counter <=0.5;
wavey <=0;
end
else
begin
if(counter >= increment)
begin
counter <= 0;
wavey <= wavey ^ 1'b1;
end
else
counter <= counter + 0.5;
end
end
endmodule